MB Lab Technology

Software — pcbtest

PCB Test Analysis

Will this board be testable before you cut the fixture?

Available 1.4.2 pcbtest — command line and desktop app

What it does

Reads the schematic netlist and the layout, works out where a fixture probe can land on every net, suggests test points where one cannot, and estimates test coverage for each component in each test process. The Excel export has one row per component.

  • Probe access per net, against your own fixture design rules
  • Suggested test points where no probe can currently land
  • Per-component coverage for ICT, flying probe, boundary scan, AOI and functional test, scored PCOLA/SOQ
  • Reads KiCad, and Altium, Eagle, PADS and CADSTAR - plus IPC-D-356 netlists and a BOM when that is all there is
  • Boundary-scan coverage from the BSDL files of the JTAG devices in your part library
  • One Excel workbook with fifteen sheets, not one table: component coverage, PCOLA/SOQ detail across every process, net access, test points, ICT probes, the AOI list, a design snippet, and five fixture sheets - plates, push rods and forces
  • Fixture plate files, per plate, on one datum - a clean machining DXF, a dimensioned drawing in DXF and SVG, an Excellon drill file, hole centres as CSV and XYZ, a probe list with the net and target of every pin, the plate as a KiCad board, and a STEP model of it for the mechanical assembly (the STEP is exported through kicad-cli, so that one needs KiCad installed; the rest are written natively)
  • A paste-ready design.py snippet, so the suggested test points go back into the layout instead of into a meeting
  • A component list in AOI Inspector's own import format, so the optical inspection starts from the same board
  • A self-contained HTML report, and batch runs across every board in a folder
  • Runs as a release gate in a build script, with an exit code
Net access and per-process coverage for the Z-Stack Controller Carrier. Red rows are nets no probe can reach, with the reason on the row.
Net access and per-process coverage for the Z-Stack Controller Carrier. Red rows are nets no probe can reach, with the reason on the row.
The same board drawn from underneath, mirrored, the way a fixture builder looks at it. Hollow rings are where an ICT probe can land, squares are pads on nets with no probe access at all, and TPS1 to TPS3 are test points the tool is suggesting to fix that. The header scores every process separately - 90.2 % combined, but boundary scan 0 % because this board has no JTAG chain. 62 parts, 45 nets, analysed in 158 ms.
The same board drawn from underneath, mirrored, the way a fixture builder looks at it. Hollow rings are where an ICT probe can land, squares are pads on nets with no probe access at all, and TPS1 to TPS3 are test points the tool is suggesting to fix that. The header scores every process separately - 90.2 % combined, but boundary scan 0 % because this board has no JTAG chain. 62 parts, 45 nets, analysed in 158 ms.
One row per component, which is also what the Excel export looks like: coverage for the component and for its joints, scored separately for in-circuit, flying probe, boundary scan, optical and functional test, then combined, then combined again assuming the suggested test points are added. The right-hand column is the useful one - it says what to do. The pane below scores PCOLA/SOQ per process and explains each verdict: this resistor is unreachable by boundary scan because the board has no scan devices, and power-on will fail without it because it sits in the power path.
One row per component, which is also what the Excel export looks like: coverage for the component and for its joints, scored separately for in-circuit, flying probe, boundary scan, optical and functional test, then combined, then combined again assuming the suggested test points are added. The right-hand column is the useful one - it says what to do. The pane below scores PCOLA/SOQ per process and explains each verdict: this resistor is unreachable by boundary scan because the board has no scan devices, and power-on will fail without it because it sits in the power path.
Three test points suggested, each quantified. Not just where, but what it costs to add - a new pad and via, or just enlarging a via pad and opening the mask - and what it buys: +2.1 % in-circuit coverage, and the specific parts it brings into reach. The coordinates are given absolute and relative, and the whole thing copies out as a design.py snippet or CSV, so the fix goes back into the layout rather than into a meeting.
Three test points suggested, each quantified. Not just where, but what it costs to add - a new pad and via, or just enlarging a via pad and opening the mask - and what it buys: +2.1 % in-circuit coverage, and the specific parts it brings into reach. The coordinates are given absolute and relative, and the whole thing copies out as a design.py snippet or CSV, so the fix goes back into the layout rather than into a meeting.
The probe list a fixture shop can actually work from: every probe numbered, with its net, side, position in millimetres, the pin it lands on and the probe size chosen for the space available - 75 mil where the nearest neighbour is 2.5 mm away, 100 mil where there is room. This is the list the bed-of-nails plate on the hardware page is drilled from.
The probe list a fixture shop can actually work from: every probe numbered, with its net, side, position in millimetres, the pin it lands on and the probe size chosen for the space available - 75 mil where the nearest neighbour is 2.5 mm away, 100 mil where there is room. This is the list the bed-of-nails plate on the hardware page is drilled from.

On video

One recording of it actually running.

A screenshot of a program that moves is only half of it, so here it is moving. Recorded off the screen while it ran on this bench - its own window, its own example project, nothing staged. One line of the toolbar, holding a path on this machine, is blurred; nothing else is altered. Nothing plays until you press it.

28 s The Z-Stack carrier analysed - 62 parts and 45 nets in 226 milliseconds - and then the parts of the answer that matter. Nets and access, where every net says whether a probe can reach it and, when it cannot, why: a pad not exposed on the bottom, a via tented over. Then the board with its probe targets marked, and the fixture plate itself with the pin table and the spring forces beside it.

Get in touch

PCB Test Analysis is not a download. It is one of the tools the work is done with, installed and licensed when an engagement starts. Tell me what you are working on and I will tell you what it would do for it.

Or email mblab.technology@gmail.com. Your details are used to answer you and to follow up — nothing else.

Requirements

  • Windows 10 or 11, 64-bit
  • About 200 MB of disk
  • No .NET install needed — the runtime is bundled
  • No Excel needed — workbooks are written directly

Also in the set

EMC Design CompatibilityFind the emissions failure on your bench, not in a rented chamber.Validation TestingHow many samples, which tests, how long, how much.Test Spec EcosystemOne traceability model across every document the product has.